Switched mode power converters are ubiquitous and are often used to convert one form of power to another. For example a Boost converter may be employed in an electronic system to convert a high voltage alternating current (AC) bus (e.g., 220 volts AC) to a higher voltage direct current (DC) bus (e.g., 400 volts DC) that may power a component such as a desktop computer or flat panel TV. Switched mode power converters have three basic figures of merit: cost, size and efficiency. To be accepted in large volume applications, power converters must meet minimum requirements for all three specifications.
Power loss in a switch, or field-effect transistor (FET) employed in switched mode power converters comes from two sources. FETs have a resistive element, that dissipates power as current is conducted through the device. The resistive parameter is typically called “on-resistance”, or RDS(ON) (i.e., resistance from drain to source when the FET is biased on). These conduction losses are inversely proportional to the size of the FET (i.e., the larger the FET, the lower its RDS(ON) and, therefore, the lower its conduction loss). The other source of power loss is through switching losses. Every time a solid-state switch is turned on or off there is energy loss, as described in more detail below.
Increased switching frequency has been a significant factor in the improvement in the cost and size of switched mode power converters. Increased switching frequency typically reduces the size of peripheral components and provides improved transient response for demanding applications. However, as discussed above, increased switching frequency results in increased power loss and decreased efficiency for the power converter.
Two major factors contribute to power loss from switching the transistors: turn-on loss, or the energy used to discharge drain-source capacitance (also commonly referred to as output capacitance or Coss); and crossover loss, or the energy lost during turn-on and turn-off transitions (i.e., the current and voltage overlap area as the switch transitions between states).
With regard to output capacitance, or Coss, as the FET switches on and off with a voltage potential across it, its intrinsic parasitic capacitance stores and then dissipates energy during each switching transition. Essentially there is an embedded capacitor within the switch that must be charged and discharged with each switching cycle. The output capacitance losses are proportional to the voltage across the switch, the switching frequency and the value of the parasitic capacitance. As the physical size of the FET increases, its output capacitance also increases. Therefore, as discussed above, increasing FET size may reduce RDS(ON), however it also increases output capacitance and thus increases switching loss.
Many types of control modes for Boost converter circuits exist that include continuous conduction mode (CCM), discontinuous conduction mode (DCM) and critical-conduction mode (CrCM) also known as boundary mode (BM). For CrCM, full ZVS is already achieved at low AC line voltage input levels (e.g., 120 VAC). At high AC line voltage input levels (e.g., 220 VAC) non-ZVS (or partial ZVS) occurs resulting in increased switching losses. Many ZVS schemes have been proposed for reducing the voltage potential across the switch to near 0 prior to operating the switch. These ZVS schemes have not been widely adopted as the increased switching losses are still acceptable for overall system efficiency requirements at operating frequencies lower than 200 kHz. At higher switching frequencies (e.g., >500 kHz) the switching losses due to partial-ZVS become significant and therefore limit the maximum allowable operating frequency of the system. Limitation of the maximum switching frequency then prevents further reduction of the boost inductor size and prevents further increase in the overall power density of the power converter.
Silicon devices have a relatively large output capacitance (Coss) (e.g., 200 picofarads) which takes a relatively long amount of time to charge. In high frequency applications, the time required to charge the output capacitance may limit the switching frequency of the converter. Further, silicon devices switch relatively slowly, (e.g., on the order of 20 nanoseconds) which also limits the switching frequency. Yet further, silicon devices are vertical structures typically fabricated such that the substrate is a drain terminal. Thus they do not lend themselves easily to monolithic integration with other devices as the other devices would be fabricated on the drain connection. This significantly restricts packaging and integration options to save packaging cost and size. Thus, in a two switch silicon-based power converter each switch is typically a separate device. The switch driver and controller circuits are also typically separate devices further increasing costs and increasing the driver delay due to packaging parasitics. Moreover, especially for high voltage applications (i.e., greater than 100 volts), silicon devices have poor performance characteristics and require large, slow, expensive driver circuits to operate. These and other factors have limited the adoption of ZVS architectures for silicon-based high frequency, high voltage applications.